The invention relates to a CMOS inverter comprised of a series connection of a normally off p-channel MOS-FET and a normally off n-channel MOS-FET whose common drain connection represents an output of the inverter.
There are instances of CMOS circuits in which different operating voltages are necessary. For example, in electrically erasable and programmable memories (E.sup.2 PROMS) CMOS-inverters whose operating voltage lies in a so-called high-voltage range of around 20 V (for example, clearly above a so-called low voltage operating voltage of around 5 V), bust be activated by low voltage inverters. The p-channel MOS-FET of a high voltage inverter, however, on account of the maximum output voltage of the low voltage inverter being too low, can thus not be blocked so that a static forward current flows.